This invention relates to an image display apparatus for displaying an expanded image by scanning the screen according to the image data read out of the memory.
An image display apparatus for displaying picture images by scanning the screen is synchronized with a vertical synchronizing signal for synchronizing fields, a horizontal synchronizing signal for synchronizing scanning lines, and a pixel synchronizing signal to output a succession of frames on the screen.
FIG. 6 shows a conventional image display apparatus by such synchronized scanning, which includes a memory 1 for storing image data, a memory control section 2 for controlling the memory 1, a processor 3 for generating the image data to be stored in the memory 1, a magnifying section 4 for expanding the image data from the processor 3 and feeding the expanded image data to the memory 1, a shift register for breaking down the image data from the memory 1 into picture elements (pixels), an oscillator 6 for generating the same frequency as the pixel frequency of a display, a vertical address counter 7 responsive to a horizontal synchronizing signal to count the number of scanning lines, and a horizontal address counter 8 responsive to a pixel synchronizing signal to count the number of pixel positions.
In operation, the processor 3 feeds the magnifying section 4 with the picture image data to be displayed. The magnifying section 4 feeds the memory 1 with the magnified or expanded image data and the memory control section 2 with a write request signal. In response to this write request signal, the memory control section 2 writes the image data on the memory 1.
The image data written in the memory 1 is displayed as follows. When a vertical synchronizing signal indicative of the start of a field is applied to the vertical address counter 7 via an input terminal 9, the vertical address counter 7 is initialized to a value equal to (the first vertical address-1). A horizontal synchronizing signal for synchronizing the scanning line to be displayed is applied to both the vertical address counter 7 and the horizontal address counter 8 via an input terminal 10. In response to this horizontal synchronizing signal, the vertical address counter 7 is incremented by one address while the horizontal address counter 8 is initialized to the first horizontal address. The vertical and horizontal memory addresses thus initialized are applied to the memory control section 2. The memory control section 2 feeds these addresses to the memory 1 to read out the contents from the memory 1 and feed them to the shift register 5. The shift register 5 breaks down the readout data into pixels with a clock signal generated by the oscillator 6 so as to have a frequency equal to the display frequency and presents the pixels at an output terminal 11. When the shift register 5 outputs all the pixels, the horizontal address counter 8 is incremented in response to a clock signal of the oscillator 6 so that the next memory address is applied to the memory control section 2. In this way, the display operation continues.
FIG. 7(a) shows a relationship between the horizontal synchronizing signal and the clock signal when no expanding operation is performed in the magnifying section 4, while FIG. 7(b) shows a similar relationship when the image data is expanded both vertically and horizontally with a magnification of 2 in the magnifying section 4 before the display data is written in the memory 1.
With such a conventional image display apparatus as described above, however, the picture image must be expanded before storage of the image memory, thus requiring an additional time for the display process. In addition, a complicated magnifying device is required.